The electronics industry is continuously increasing the amount of logic circuits needed to fulfill advanced tasks which has lead to complex topologies for multi-input logic circuits. For example, common practice for doing n-way (n-input) XOR/XNOR logic gates (while n>=3) is to use a number of cascaded stages of 2-way XOR/XNOR circuits in which the output of one XOR or XNOR stage is serially connected to the input of a subsequent XOR or XNOR stage. An example of such cascaded XOR gates is described in U.S. Pat. No. 7,231,572 B2 to Clark, which teaches constructing an XOR logic tree for testing integrated circuitry. However, when serially connecting multiple stages of XOR or XNOR gates, a complex arrangement of PFETs and NFETs is required which is non-optimal for efficient use of available circuit area and which may produce undesirable sensitivity to noise and reduction in processing speed. Thus, more efficient logic topologies are desirable which are less sensitive to noise, offer improved speed of operation, and make more efficient use of available circuit area.